View STE2002_77029.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STE2002
81 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
s s s s s s s s
104 x 128 bits Display Data RAM Programmable MUX rate Programmable Frame Rate X,Y Programmable Carriage Return Dual Partial Display Mode Row by Row Scrolling Automatic data RAM Blanking procedure Selectable Input Interface: * I2C Bus Fast and Hs-mode (read and write) * Parallel Interface (read and write) * Serial Interface (read and write) Fully Integrated Oscillator requires no external components CMOS Compatible Inputs Fully Integrated Configurable LCD bias voltage generator with: * Selectable multiplication factor (up to 6X) * Effective sensing for High Precision Output * Eight selectable temperature compensation coefficients Designed for chip-on-glass (COG) applications
s s s s s
Low Power Consumption, suitable for battery operated systems Logic Supply Voltage range from 1.7 to 3.6V High Voltage Generator Supply Voltage range from 1.75 to 4.2V Display Supply Voltage range from 4.5 to 11V Backward Compatibility with STE2001
DESCRIPTION The STE2002 is a low power CMOS LCD controller driver. Designed to drive a 81 rows by 128 columns graphic display, provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. The STE2002 features three standard interfaces (Serial, Parallel & I2C) for ease of interfacing with the host mcontroller.
Type Bumped Wafers Bumped Dice on Waffle Pack Ordering Number STE2002DIE1 STE2002DIE2
s s s
s
Figure 1. Block Diagram
CO to C127 R0 to R80 ICON
OSC_IN OSC_OUT
OSC
TIMING GENERATOR CLOCK
COLUMN DRIVERS
ROW DRIVERS
VLCDIN
BIAS VOLTAGE GENERATOR
DATA LATCHES
SHIFT REGISTER
VLCDSENSE VLCDOUT
HIGH VOLTAGE GENERATOR
RES VSSAUX VDD1,2 VSS SEL1,2
RESET
104 x 128 RAM
SCROLL LOGIC TEST_1_14 TEST
DATA REGISTER
INSTRUCTION REGISTER
DISPLAY CONTROL LOGIC
ICON_MODE EXT BSY_FLG
SA1
I2CBUS
SOUT PARALLEL SERIAL
SAO
SCL
SDA_IN
SDA_OUT DB0 to DB7 E
R/W PD/C SCE
SDIN
SCLK
SD/C
September 2002
1/51
STE2002
PIN DESCRIPTION
N R0 to R80 ICON C0 to C127 VSS VDD1 VDD2 VLCDIN VLCDOUT VLCDSENSE VSSAUX SEL1,2 EXT Pad 129-169 282-322 323 1-128 236-255 188-199 200-211 261-270 273-282 271-272 180, 231, 218 184,185 183 Type O O O GND Supply Supply Supply Supply Supply O I I LCD Row Driver Output ICON Row Driver LCD Column Driver Output Ground pads. IC Positive Power Supply Internal Generator Supply Voltages. LCD Supply Voltages for the Column and Row Output Drivers. Voltage Multiplier Output Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning Ground Reference for Selection Pins Configuration Interface Mode Selection Extended Instruction Set Selection EXT PAD CONFIG VSS or VSSAUX VDD1 ICON_MO DE 186 I ICON ROW Management ICON MODE PAD CONFIG VSS or VSSAUX VDD1 SDA_IN SDA_OUT SCL SA0 SA1 OSCIN OSCOUT RES DB0 to DB7 R/W E PD/C SDIN 234 232 235 182 181 187 260 230 220-227 219 229 228 214 I O I I I I O I I/O I I I I I2C Bus Data In I2C Bus Data Out I2C bus Clock I2C Slave Address BIT 0 I2C Slave Address BIT 1 External Oscillator Input Internal/External Oscillator Out Reset Input. Active Low. Parallel Interface 8 Bit Data Bus Parallel Interface Read & Write Control Line Parallel Interface Data Latch Signal. Parallel Interface Data/Command Selector Serial Interface Data Input ICON MODE STATUS DISABLED ENABLED Function
INSTRUCTION SET SELECTED BASIC EXTENDED
2/51
STE2002
PIN DESCRIPTION (continued)
N SCLK SCE SD/C SOUT BSYFLG T1 to T14 Pad 217 216 215 213 212 170-179, 256-259 Type I I I O O I/O Serial Interface Clock Serial Interface ENABLE. When Low the Incoming Data are Clocked In. Serial Interface Data/Command Selector Serial Out Active Procedure Flag. Notice if There is an ongoing Internal Operation or an active reset. Active Low. Test Pads. - A 50kohm pull-down resistor is added on input pis. Test Num. TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 TEST_8 TEST_9 TEST_10 TEST_11 TEST_12 TEST_13 TEST_14 Pin Configuration OPEN Function
VSS / VSSAUX
VSS / VSSAUX
3/51
STE2002
Figure 2. Chip Mechanical Drawing
ICON ROW 0 ROW 34
MARK_1
COL
0
ROW 35
ROW 39.
STE2002
VLCDOUT
VLCDOUT
VLCDSENSE
VLCDSENSE
VLCDIN
VLCDIN
MARK_3
OSCOUT
TEST_14 TEST_13 TEST_12 TEST_11
VSS
SCL SDAIN SDAOUT COL 63 VSSAUX
(0,0)
COL 64
RES
Y
X
E PD/C D0 D1 D2 D3 D4 D5 D6 D7 R/W VSSAUX SCLK SCE SD/C SDIN SDOUT
MARK_4
BSY_FLG
VDD2
VDD2
VDD1
VDD1
OSCIN ICON_MODE SEL1 SEL2 EXT_SET SA0 SA1 VSSAUX TEST_10 TEST_9 TEST_8 TEST_7 TEST_6 TEST_5 TEST_4 TEST_3 TEST_2 TEST_1
ROW 80/ICON ROW 79
COL 127
MARK_2
ROW 76
ROW 40
4/51
ROW 75
STE2002
Figure 3. Improved ALTH & PLESKO Driving Method
VLCD V2 V3 ROW 0 R0 (t) V4 V5 VSS VLCD V2 V3 ROW 1 R1 (t) V4 V5 VSS VLCD V2 V3 COL 0 C0 (t) V4 V5 VSS VLCD V2 V3 COL 1 C1 (t) V4 V5 VSS VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS V4 - V5 0V VSS - V5 V4 - VLCD VSS - VLCD V1(t) V2(t)
Vstate1(t)
VLCD - VSS V3 - VSS VLCD - V2 0V V3 - VSS
Vstate2(t)
V4 - V5 0V VSS - V5
V4 - VLCD VSS - VLCD
0 1 2 3 4 5 6 7 8 9 ....... ..... 64 0 1 2 3 4 5 6 7 8 9 ....... ..... 64
FRAME n V1(t) = C1(t) - R0(t) V2(t) = C1(t) - R1(t)
FRAME n + 1
D00IN1154
5/51
STE2002
CIRCUIT DESCRIPTION Supplies Voltages and Grounds VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to V DD1 pad. VDD1 supplies the rest of the IC. V DD1 supply voltage could be different form VDD2. Internal Supply Voltage Generator The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplying factor can be programmed to be: Auto, X6, X5, X4, X3, X2, using the 'set CP Multiplication' Command. If Auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. This make possible to have an input voltage that changes over time and a constant VLCD voltage. The output voltage (VLCDOUT) is tightly controlled through the VLCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using the bits TC1 and TC0 and T2,T1 & T0. This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the VLCDIN and VLCDOUT pads must be connected together. An external supply could be connected to VLCDIN to supply the LCD without using the internal generator. In such event the VLDCOUT and VLCDSENSE must be connected to GND and the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition). Oscillator A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be used and fed into the OSC pin. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers Bias Levels To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to be (Fig. 4): n+2 2 1 n+3 V L CD, ------------ V LCD , ------------ V LCD , ------------ V L CD , ------------ V LCD ,V SS n+4 n+4 n+4 n+4 Figure 4. Bias level Generator
R VLCD n+3 *VLCD n+4 R n+2 *VLCD n+4 nR 2 *VLCD n+4 R 1 *VLCD n+4 R VSS
D00IN1150
thus providing an 1/(n+4) ratio, with n calculated from: n= For m = 81, n = 6 and an 1/10 ratio is set. For m = 65, n =5 and an 1/9 ratio is set. m-3
6/51
STE2002
The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0
The following table Bias Level for m = 65 and m = 81 are provided:
Symbol V1 V2 V3 V4 V5 V6 m = 65 (1/9) VLCD 8/9*VLCD 7/9*VLCD 2/9*V VLCD 1/9 *VLCD VSS m = 81 (1/10) VLCD 9/10*VLCD 8/10*VLCD 2/10*VLCD 1/10*VLCD VSS
LCD Voltage Generation The LCD Voltage at reference temperature (To = 27C) can be set using the VOP register content according to the following formula: VLCD(T=To) = VLCDo = (Ai+VOP * B) with the following values:
Symbol Ao A1 A2 B To Value 2.95 6.83 10.71 0.0303 27 Unit V V V V C Note PRS = [0;0] PRS = [0;1] PRS = [1;0]
(i=0,1,2)
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits are set to zero the internal voltage generator is switched off. The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing Rate. A general expression for this is: 1+ m V L CD = ----------------------------------- V th 1 2 1 - -------m For MUX Rate m = 65 the ideal VLCD is: VLCD(to) = 6.85 * Vth than: ( 6.85 Vth - A i ) V o p = ---------------------------------------0.03

7/51
STE2002
Temperature Coefficient As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. The STE2002 provides the possibility to change the VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable through the T2, T1 and T0 bits. Only four of them are available with basic instruction set (TC1 & TC0 Bits).
NAME TC0 TC2 TC3 TC6 TC1 0 0 1 1 TC0 0 1 0 1 Value -0.0* 10-3 -0.7 * 10-3 -1.05* 10-3 -2.1 * 10-3 Unit 1/ C 1/C 1/C 1/C
NAME TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
TC2 0 0 1 1 1 1 1 1
TC1 0 1 0 1 1 1 1 1
TC0 0 1 0 1 1 1 1 1
Value -0.0* 10-3
Unit 1/ C 1/C 1/C 1/C 1/C 1/C 1/C 1/C
-0.35 * 10-3 -0.7 * 10-3 -1.05* 10-3 -1.4 * 10-3 -1.75* 10-3 -2.1 * 10-3 -2.3* 10-3
Figure 5.
VLCD
B A0 + B A0
00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h ....
A2 A1
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h .... 7Ch 7Dh 7Eh 7Fh
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
VO
Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD(T) = VLCDo * [1 + (T-To) * TC]
8/51
STE2002
Display Data RAM The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y12 (Vertical). When writing to RAM, four addressing mode are provided: * Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 6) * Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 7). * Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=XCarriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 8). * Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 9). After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13). Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the bottom (D0=1, Fig. 15). The STE2002 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory RAM. It is only related to the visualization process. When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON Mode=0 the Icon Row is like the other graphic lines and is mirrored and scrolled. Four are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49, MUX 65 and MUX 81). Only a subset of writable rows are output on Row drivers. When Y-CarriageMUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to select which lines of DDRAM are connected on the output drivers. The DDRAM rows to visualized can be selected in the 0-Y-Carriage*8 range using the scrolling function. When Y-Carriage>MUX lines, the icon row is moved in DDRAM to the first row of the Y-CARRIAGE Return BANK even if it is always connected on the same output Driver. When MY=0, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on R64 in MUX49 and on R56 in MUX 33. When MY=1, and ICON MODE=1, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on R64 in MUX49 and on R56 in MUX 33. When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate. When ICON MODE =1, the Memory ICON Row content is output on ICON Pad. If Not Used ICON Pad must be left floating.
9/51
STE2002
Figure 6. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1
0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12
1
2
3
124
125
126
127
Figure 7. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1
0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12
1
2
3
124
125
126
127
Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1
127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12
126
125
124
3
2
1
0
Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1
127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12
126
125
124
3
2
1
0
1. X Carriage=127; Y-Carriage = 12
10/51
STE2002
Figure 10. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=0)
X CARR
0 BANK 0 BANK 1 BANK 2
1
2
3
124
125
126 127
Y CARR
BANK 11 BANK 12
Figure 11. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=0)
X CARR 0 BANK 0 BANK 1 BANK 2 1 2 3 124 125 126 127
Y CARR
BANK 11 BANK 12
Figure 12. Automatic data RAM writing sequence with X-Y Carriage Return (V=0; MX=1)
X CARR 127 BANK 0 BANK 1 BANK 2 126 125 124 3 2 1 0
Y CARR
BANK 11 BANK 12
Figure 13. Automatic data RAM writing sequence with X-Y Carriage Return (V=1; MX=1)
X CARR 127 BANK 0 BANK 1 BANK 2 126 125 124 3 2 1 0
Y CARR
BANK 11 BANK 12
11/51
STE2002
Figure 14. Data RAM Byte organization with D0 = 0
MSB 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 1 2 3 124 125 126 127
LSB
Figure 15. Data RAM Byte organization with D0 = 1
LSB 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 1 2 3 124 125 126 127
MSB
Figure 16. Memory Rows vs. Row drivers mapping with MY=0, MUX81, ICON MODE=0,1
ROW DRIVER ICON MODE=1 ROW DRIVER ICON MODE=0 PHYSICAL MEMORY ROW
0 R0 R1 R2 R3 R0 R1 R2 R3 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE
R 79 R 80 ICON
R 79 R 80
ROW 79 ROW 80
ICON ROW
Figure 17. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER = +3, ICON MODE=1
ROW DRIVER ICON MODE=1 PHYSICAL MEMORY ROW
0 R0 R1 R2 R3 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE R 76 R 77 R 78 R 79 R 80 ICON
ROW 79 ROW 80
ICON ROW
12/51
STE2002
Figure 18. Memory Rows vs. Row drivers mapping with MY=0, MUX 81, SCROLL POINTER=+3, ICON MODE=0
ROW DRIVER ICON MODE=0 PHYSICAL MEMORY ROW
0 R0 R1 R2 R3 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE R 76 R 77 R 78 R 79 R 80 ICON
ROW 79 ROW 80 ROW 161
ICON ROW
Figure 19. Memory Rows vs. Row drivers mapping with MUX 65 Y-CARRIAGE<=8 SCROLL POINTER=0, ICON MODE=1
ROW DRIVER
PHYSICAL MEMORY ROW
0 R0 R 30 R 31 N.C. R 40 R 71 R 72 ROW 31 ROW 32 ROW 63 ROW 64 ROW 0 ROW 1
1
2
3
124
125
126
127
Y-CARRIAGE ICON ROW
N.C.
R 79 R 80 ICON
ROW 96
Figure 20. Memory Rows vs. Row drivers mapping with MUX65, Y-CARRIAGE>8, SCROLL POINTER=0, ICON MODE=1
ROW DRIVER PHYSICAL MEMORY ROW
0 R0 R 31 R 32 N.C. R 40 R 71 R 72 ROW 75 ROW 76 R 79 R 80 ICON ROW 96 ROW 63 ROW 0 ROW 31 ROW 32
1
2
3
124
125
126
127
ICON ROW
Y-CARRIAGE
N.C.
13/51
STE2002
Figure 21. Memory Rows vs. Row drivers mapping with MUX65, Y-CARRIAGE>8, SCROLL POINTER=3, ICON MODE=1,
ROW DRIVER PHYSICAL MEMORY ROW
0 R0 R 30 R 31 N.C. R 40 R 71 R 72 ROW 0 ROW 1 ROW 2 ROW 33 ROW 34 ROW 66 ROW 75 ROW 76 R 79 R 80 ICON ROW 96
1
2
3
124
125
126
127
ICON ROW
Y-CARRIAGE
N.C.
Figure 22. Memory Rows vs. Row drivers mapping with MY=1, MUX81, ICON MODE 0,1 SCROLL POINTER=0
ROW DRIVER ICON MODE=1
ROW DRIVER ICON MODE=0
PHYSICAL MEMORY ROW
0 R 79 R 78 R 80 R 79 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE
R2 R1 R0 R 80 ICON
R3 R2 R1 R0 ICON
ROW 79 ROW 80
ICON ROW
Figure 23. Memory Rows vs. Row drivers mapping with MY=1, MUX81, SCROLL OFFSET= +3, ICON MODE =0
ROW DRIVER ICON MODE=0 PHYSICAL MEMORY ROW
0 R 80 R 78 R 79 R 77 R 76 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE
R1 R0 ICON
ROW 79 ROW 80
ICON ROW
14/51
STE2002
Figure 24. Memory Rows vs. Row drivers mapping with MY=1, MUX81, SCROLL OFFSET= +3, ICON MODE =1
ROW DRIVER ICON MODE=1 PHYSICAL MEMORY ROW SCROLL OFFSET +3
0 R 79 R 78 R 77 R 76 ROW 0 ROW 1 ROW 2 ROW 3
1
2
3
124
125
126
127
Y-CARRIAGE
R1 R0 R 80 ICON
ROW 79 ROW 80
ICON ROW
Figure 25. Row Drivers vs. LCD Panel Interconnection in MUX81 Mode
ICON
81x128 MUX 81 Mode
COLUMN DRIVERS
R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75
ROW DRIVERS
STE2002
R80/ICON R79 R78 R77 R76 R35 R36 R37 R38 R39
ICON R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34
ROW DRIVERS
LR0012
15/51
STE2002
Figure 26. Row Drivers vs. LCD Panel Interconnection in MUX65 Mode
ICON
65x128 MUX 65 Mode
COLUMN DRIVERS
R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75
ROW DRIVERS
STE2002
R80/ICON R79 R78 R77 R76 R35 R36 R37 R38 R39
ICON R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34
ROW DRIVERS
LR0014
Figure 27. Row Drivers vs. LCD Panel Interconnection in MUX49 Mode
ICON
49x128 MUX 49 Mode
COLUMN DRIVERS
R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75
ROW DRIVERS
STE2002
R80/ICON R79 R78 R77 R76 R35 R36 R37 R38 R39
ICON R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34
ROW DRIVERS
LR0013
16/51
STE2002
Figure 28. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode
ICON
33x128 MUX 33Mode
COLUMN DRIVERS
R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75
ROW DRIVERS
STE2002
R80/ICON R79 R78 R77 R76 R35 R36 R37 R38 R39
ICON R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34
ROW DRIVERS
LR0106
Instruction Set Two different instructions formats are provided: - With D/C set to LOW commands are sent to the Control circuitry. - With D/C set to HIGH the Data RAM is addressed. Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect to VSS). To select the extended instruction the EXT pad has to be connected to a logic HIGH (connect to VDD1). The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set) Reset (RES) At power-on, all internal registers are configured with the default value. The RAM content is not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6). Applying a reset pulse, every on-going communication with the host controller is interrupted. After the power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal registers The Default configurations is: . - Horizontal addressing (V = 0) - Normal instruction set (H[1:0] = 0) - Normal display (MX = MY = 0) - Display blank (E = D = 0) - Address counter X[6: 0] = 0 and Y[4: 0] = 0 - Temperature coefficient (TC[1: 0] = 0) - Bias system (BS[2: 0] = 0) - Multiplexing Ratio (M[1:0]=0) - Frame Rate (FR[1:0]="75Hz") - Power Down (PD = 1) - Dual Partial Display Disabled (PE=0) - VOP=0
A MEMORY BLANK instruction can be executed to clear the RAM content.
17/51
STE2002
Power Down (PD = 1) When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared. Memory Blanking Procedure This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (128X13) single "write" instructions. It is possible to program "Memory Blanking Procedure" only under the following conditions: - PD bit =0 The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is running). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface). Checker Board Procedure This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. It is possible to program "Checker Board Procedure" only under the following conditions: - PD bit =0 The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running. Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles (128X13X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface). Scrolling function The STE2002 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn't affect the data ram content. It is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range changes in accordance with MUX Rate. After 80th/81th scrolling commands in MUX 81 mode, or after the 64th/65th scrolling commands in mux 65 mode, or after 48nd/49rd scrolling command in MUX 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory address and the memory scanning pointer The Icon Row is not scrolled if ICON MODE =1. If ICON MODE=0 the last row is like a general purpose row and it is scrolled as other rows. If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.
18/51
STE2002
OFFSET RANGE 0-31 0-32 0-47 0-48 0-63 0-64 0-79 0-80 ICON Row Driver with MY=0 R56 R56 R64 R64 R72 R72 R80 R80
MUX RATE MUX 33 MUX 33 MUX 49 MUX 49 MUX 65 MUX 65 MUX 81 MUX 81
ICON MODE 1 0 1 0 1 0 1 0
DESCRIPTION ICON ROW NOT SCROOLED 33 LINE GRAPHIC MATRIX ICON ROW NOT SCROOLED 49 LINE GRAPHIC MATRIX ICON ROW NOT SCROOLED 65 LINE GRAPHIC MATRIX ICON ROW NOT SCROOLED 81 LINE GRAPHIC MATRIX
Dual Partial Display If the PE Bit is set to a logic one the dual partial display mode is enabled. Eight partial display modes are available. The offset of the two partial display zones is row by row programmable. The Icon row is accessed last in each partial display frame. Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].). This allows switching from normal mode to partial display mode applying one instruction. The HV generator is automatically re configured using the parameters related to the enabled mode. The parameters of the two sets of registers with the same function are located in the same position of the instruction set. The registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] values the instruction flow proposed in Fig.46 must be followed. To setup Partial Display Sectors Start Address and Partial Display Mode no particular instruction flow has to be followed. .
PD2 0 0 0 0 1 1 1 1 PD1 0 0 1 1 0 0 1 1 PD0 0 1 0 1 0 1 0 1 SECTION 1 0 8 8 0 16 8 16 16 SECTION2 8 + Icon Row 0 + Icon Row 8 + Icon Row 16 + Icon Row 0 + Icon Row 16 + Icon Row 8 + Icon Row 16 + Icon Row 000 RESET STATE
19/51
STE2002
Bus Interfaces To provide the widest flexibility and ease of use the STE2002 features three different methods for interfacing the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. All interfaces are working while the STE2002 is in Power Down .
SEL2 0 0 1 1 SEL1 0 1 0 1 Interface I2C Serial Parallel Note Read and Write; Fast and High Speed Mode Read and Write Read and Write Not Used
I2C Interface The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted bytewide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an endof-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP
20/51
STE2002
condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2002 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2002 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code. Figure 29. Bit transfer and START,STOP conditions definition
DATA LINE STABLE DATA VALID CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
D00IN1151
STOP CONDITION
Figure 30. Acknowledgment on the I2C-bus
START SCLK FROM MASTER CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER
MSB
LSB
D00IN1152
Communication Protocol The STE2002 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1. To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, shown in Fig. 30, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W). All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer. Writing Mode. If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves acknowledge one or more command word follows to define the status of the device. A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,
21/51
STE2002
the second is a data byte (fig 31). The Co bit is the command MSB and defines if after this command will follow one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/ C = 0 Command). If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following data byte will be stored in the data RAM at the location specified by the data pointer. Every byte of a command word must be acknowledged by all addressed units. After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2002 Display RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every byte written and in the end points to the last RAM location written. Every byte must be acknowledged by all addressed units. Reading Mode. If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent during the last write access, is set to a logic 0, the byte read is the status byte. Figure 31. Communication Protocol
WRITE MODE STE2002 ACK STE2002 ACK STE2002 ACK STE2002 ACK STE2002 ACK
SS S 0 1 1 1 1 A A 0 A 1 DC Control Byte A 10 R/W Co SLAVE ADDRESS READ MODE STE2002 ACK SS S01111AA1A 10 R/W
DATA Byte
A 0 DC Control Byte A
DATA Byte
AP
Co COMMAND WORD
LAST CONTROL BYTE
N> 0 BYTE MSB........LSB
MASTER ACK SSR 01111AA / 1 0W STE2002 SLAVE ADDRESS
P
CD 000000A oC
CONTROL BYTE
SERIAL INTERFACE The STE2002 serial Interface is a bidirectional link between the display driver and the application supervisor. It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one for the peripheral enable (SCE) and one for mode selection (SD/C). The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral power consumption is zero. While SCE pin is high the serial interface is kept in reset. The STE2002 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge. SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the eighth SCLK clock pulse during every byte transfer.
22/51
STE2002
If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte at the next SCLK positive edge. A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal registers are cleared. If SCE is low after the positive edge of RES, the serial interface is ready to receive data. Throughout SOUT can be read only the driver I2C slave address. The Command sequence that allows to read I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance in steady state and during data write. It is possible to short circuit DOUT and SDIN and read I2C address without any additional lines. Figure 32. Serial bus protocol - one byte transmission
SCE
D/C
SCLK
SDIN
MSB
LSB
D00IN1159
Figure 33. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 34. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
DB7
DB6
DB5
D00IN1160
SOUT
High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
Command Write
I2C Address Read
23/51
STE2002
Figure 35. Reading Sequence
READING SEQUENCE
Write a "00000000" Instruction
SOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and Read the I2C Address or Status Byte On SOUT
1
SOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver 2) SDIN and SOUT can be short circuited if the processor can configure serial output buffers in high impedence during data read.
LR0078
Parallel Interface The STE2002 parallel Interface is a bidirectional link between the display driver and the application supervisor. It consists of eleven lines: eight data lines (from DB7 to DB0) and three control lines. The control lines are: enable (E) for data latch, PD/C for mode selection and R/W for reading or writing. The data lines and the control line values are internally latched on E rising edge (fig. 50). When the parallel interface is selected, if R/W line is set to "one", D0-D7 lines are configured as output drivers (low impedence) and it is possible to read the driver I2C address (Fig. 51)
24/51
STE2002
Table 1. STE2001-like instruction Set
Instruction D/C R/W B7 H=0 or H=1 0 Function Set Read Status Byte Write Data H=0 Memory Blank Scroll VLCD Range Setting Display Control Set CP Factor Set RAM Y Set RAM X H=1 Checker Board Multiplex Select TC Select Output Address Bias Ratios Reserved Set VOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 X 0 0 0 0 1 X 0 0 0 1 0 X 0 0 1 DO 0 1 1 MUX Starts Checker Board Procedure Selects MUX factor 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 X6 0 0 0 0 0 0 X5 0 0 0 0 1 0 X4 0 0 0 1 0 Y3 X3 0 0 1 D S2 Y2 X2 0 1 0 0 S1 Y1 X1 1 DIR Starts Memory Blank Procedure Scrolls by one Row UP or DOWN 0 0 1 0 0 1 0 0 0 PD D7 0 0 A1 D6 0 1 A2 D5 0 MX D D4 0 MY E D3 0 PD MX D2 0 V MY D1 0 Read I2C Address (with Serial Interface only) B6 B5 B4 B3 B2 B1 B0 Description
H[0] Power Down Management; Entry Mode; DO D0 (I2C interface only) Writes data to RAM
PRS VLDC programming range selection [0] E S0 Y0 X0 Select Display Configuration Charge Pump Multiplication factor Set Horizontal (Y) RAM Address Set Vertical (X) RAM Address
TC1 TC0 Set Temperature Coefficient for VLDC A1 A2 No function Set desired Bias Ratios Not to be used VOP register Write instruction
BS2 BS1 BS0 X X X
OP6 OP5 OP4 OP3 OP2 OP1 OP0
25/51
STE2002
Table 2. Extended Instruction Set
Instruction D/C R/W B7 NOP Function Set Read Status Byte Write Data Memory Blank Scroll VLCD Range Setting Display Control Set CP Factor Set RAM Y Set RAM X Checker Board TC Select Data Format Bias Ratios Set VOP 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Partial Mode 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD D7 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 B6 0 0 0 D6 0 0 0 0 0 1 X6 0 0 0 0 0 1 B5 0 1 0 D5 0 0 0 0 0 0 X5 0 0 0 0 0 X B4 0 MX D D4 0 0 0 0 1 0 X4 0 0 0 0 1 X B3 0 MY E D3 0 0 0 1 0 Y3 X3 0 0 0 1 0 X B2 0 PD MX D2 0 0 1 D S2 Y2 X2 0 0 1 DO X B1 0 B0 0 Read I2C Address (with Serial Interface only) Power Down Management; Entry Mode; Extended Instruction Set (I2C interface only) Writes data to RAM Starts Memory Blank Procedure Scrolls by one Row UP or DOWN VLDC programming range selection Select Display Configuration Charge Pump Multiplication factor Set Horizontal (Y) RAM Address Set Vertical (X) RAM Address Starts Checker Board Procedure Vertical Addressing Mode MSB Position Set desired Bias Ratios Reserved VOP register Write instruction Software RESET Partial Enable Frame rate Control Mux Ratio Partial Display Config 1st Sector Start Address 2nd Sector Start Address H Independent Instructions Description
H[1] H[0] MY D1 0 1 DO D0 1 DIR
H=[0;0] RAM Commands
PRS PRS [1] [0] 0 S1 Y1 X1 0 1 0 X E S0 Y0 X0 1 V 0 X
H=[0;1]
TC1 TC0 Set Temperature Coefficient for VLDC
BS2 BS1 BS0
OP6 OP5 OP4 OP3 OP2 OP1 OP0 H=[1;0] 0 0 0 0 0 1 PD Y6 0 0 0 0 0 1 0 0 0 0 0 PD Y5 PD Y5 0 0 0 0 0 0 0 0 0 0 1 PD Y4 PD Y4 0 0 0 0 1 0 0 0 0 1 0 PD Y3 PD Y3 0 0 0 1 X 0 0 1
0
0 1
1 PE
FR1 FR0 M[1] M[0] PD Y1 PD Y1 0 1 X T1 X PDY 0 PD Y0 1 X X T0 X
PD2 PD1 PD0 PD Y2 PD Y2 0 0 1 T2 X
H=[1;1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Scrolling Pointer Reset Not Used Not Used Set Temperature Coefficient for VLDC Not Used Y-CARRIAGE RETURN X CARRIAGE RETURN
YC-3 YC-2 YC-1 YC-0
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0
26/51
STE2002
Table 3. Explanations of Table 2 symbols
BIT DIR PD V MX MY DO PE H[0] MUX 0 Scroll by one down Device fully working Horizontal addressing Normal X axis addressing Image is displayed not vertically mirrored MSB on TOP Partial Display disabled Select page 0 MUX 65 1 Scroll by one up Device in power down Vertical addressing X axis address is mirrored. Image is displayed vertically mirrored MSB on BOTTOM Partial Display enabled Select page 1 MUX 33 1 0 0 0 0 0 0 0 RESET STATE
Table 4. PAGE NUMBER
H[1] 0 0 1 1 H[0] 0 1 0 1 Page 0 Page 1 Page 2 Page 3 Page 0 DESCRIPTION RESET STATE
Table 5. DISPLAY MODE
D 0 0 1 1 E 0 1 0 1 display blank all display segments on normal mode inverse video mode D=0 E=0 DESCRIPTION RESET STATE
Table 6. FRAME RATE CONTROL
FR[1] 0 0 1 1 FR[0] 0 1 0 1 DESCRIPTION 65Hz 70Hz 75Hz 80Hz 75Hz RESET STATE
Table 7. VLCD RANGE SELECTION
PRS[1] 0 0 1 1 PRS[0] 0 1 0 1 DESCRIPTION 2.94 6.78 10.62 Not Used RESET STATE
27/51
STE2002
Table 8. MULTIPLEXING RATIO
M[1] 0 0 1 1 M[0] 0 1 0 1 DESCRIPTION 49 65 81 Not Used 01 RESET STATE
Table 9. TEMPERATURE COEFFICIENT
T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 1 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 VLCD temperature Coefficient 4 VLCD temperature Coefficient 5 VLCD temperature Coefficient 6 VLCD temperature Coefficient 7 000 RESET STATE
Table 10.
TC1 0 0 1 1 TC0 0 1 0 1 DESCRIPTION VLCD temperature Coefficient 0 VLCD temperature Coefficient 2 VLCD temperature Coefficient 3 VLCD temperature Coefficient 6 00 RESET STATE
Table 11. CHARGE PUMP MULTIPLICATION FACTOR
CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 DESCRIPTION RESET STATE
Multiplication Factor X2 Multiplication Factor X3 Multiplication Factor X4 Multiplication Factor X5 Multiplication Factor X6
NOT USED NOT USED AUTOMATIC
000
Table 12. BIAS RATIO
BS2 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 DESCRIPTION Bias Ratio equal to 7 Bias Ratio equal to 6 Bias Ratio equal to 5 Bias Ratio equal to 4 Bias Ratio equal to 3 Bias Ratio equal to 2 Bias Ratio equal to 1 Bias Ratio equal to 0 000 RESET STATE
28/51
STE2002
Table 13. Y CARRIAGE RETURN REGISTER
Y-C[3] 0 0 0 0 0 0 . 1 1 1 Y-C[2] 0 0 0 0 1 1 . 0 0 1 Y-C[1] 0 0 1 1 0 0 . 1 1 0 Y-C[0] 0 1 0 1 0 1 . 0 1 0 Y-CARRIAGE =10 Y-CARRIAGE =11 Y-CARRIAGE =12 Y-CARRIAGE =1 Y-CARRIAGE =2 Y-CARRIAGE =3 Y-CARRIAGE =4 Y-CARRIAGE =5 1000 DESCRIPTION RESET STATE
Table 14. PARTIAL DISPLAY CONFIGURATION
PD2 0 0 0 0 1 1 1 1 PD1 0 0 1 1 0 0 1 1 PD0 0 1 0 1 0 1 0 1 SECTION 1 0 8 8 0 16 8 16 16 SECTION2 8 + Icon Row 0 + Icon Row 8 + Icon Row 16 + Icon Row 0 + Icon Row 16 + Icon Row 8 + Icon Row 16 + Icon Row 000 RESET STATE
29/51
STE2002
Figure 36. Host Processor Interconnection with I2C Interface
SCL SDAIN
STE2002
SDAOUT VSSAUX RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 R/W VSSAUX SCLK SCE SD/C SDIN SDOUT BSY_FLG VDD2 VDD1 OSCIN ICON_MODE SEL1 SEL2 EXT_SET SA0 SA1 VSSAUX TEST_10 TEST_9 TEST_8 TEST_7 TEST_6 TEST_5 TEST_4 TEST_3 TEST_2 TEST_1
GND / VSSAUX VDD1 VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX
P
Figure 37. Host Processor Interconnection with Serial Interface
SCL SDAIN SDAOUT VSSAUX RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 R/W VSSAUX SCLK SCE SD/C SDIN SDOUT BSY_FLG VDD2 VDD1 OSCIN ICON_MODE SEL1 SEL2 EXT_SET SA0 SA1 VSSAUX TEST_10 TEST_9 TEST_8 TEST_7 TEST_6 TEST_5 TEST_4 TEST_3 TEST_2 TEST_1
VDD1 / GND / VSSAUX VDD1 GND / VSSAUX VDD1 VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX
STE2002
P
30/51
STE2002
Figure 38. Host Processor Interconnection with Parallel Interface
SCL SDAIN
STE2002
SDAOUT VSSAUX RES E PD/C D0 D1 D2 D3 D4 D5 D6 D7 R/W VSSAUX SCLK SCE SD/C SDIN SDOUT BSY_FLG VDD2 VDD1 OSCIN ICON_MODE SEL1 SEL2 EXT_SET SA0 SA1 VSSAUX TEST_10 TEST_9 TEST_8 TEST_7 TEST_6 TEST_5 TEST_4 TEST_3 TEST_2 TEST_1
VDD1 / GND / VSSAUX GND / VSSAUX VDD1 VDD1 VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX
P
Figure 39. Application Schematic Using an External LCD Voltage Generator
I/O VDD VDD2 VDD1 100nF VSS VSS2 VSS1 1F 128 81x 128 DISPLAY
40
VLCDSENSE VLCDOUT
41
VLCD
VLCDIN
31/51
STE2002
Figure 40. Application Schematic using the Internal LCD Voltage Generator and two separate supplies
I/O VDD2 VDD1 100nF VSS VDD2 VDD1 100nF VSS2 VSS1 1F VLCDSENSE VLCDOUT VLCDIN 41 128
40
81x 128 DISPLAY
Figure 41. Application Schematic using the Internal LCD Voltage Generator and a single supply
I/O VDD
VDD2 VDD1
40
100nF VSS VSS2 VSS1 1F VLCDSENSE VLCDOUT VLCDIN 41 128
81 x 128 DISPLAY
32/51
STE2002
Figure 42. Power-Up sequence
Tvdd Tw(res) TLogic (res)
VDD2
VDD1
RES
SCE SCLK SDIN SD/C PD/C E R/W
D0 - D7 HOST
D0 - D7 DRIVER
Hi-Z
SCL SDAIN SOUT SDA OUT
Hi-Z
OSCIN (HOST)
OSC OUT (DRIVER)
BSY FLG
BOOSTER OFF RESET POWER ON TABLE INTERNAL LOADED RESET
LR0116
33/51
STE2002
Figure 43. Power-OFF Sequence
Tw(res)
VDD2
VDD1
RES SCLK SDIN SD/C PD/C E SCE SCl SDAIN
R/W
D0 - D7 HOST
D0 - D7 DRIVER
Hi-Z
SOUT SDA OUT
Hi-Z
OSCIN (HOST)
OSC OUT (DRIVER)
BSY FLG
RESET TABLE LOADED
LR0117
34/51
STE2002
Figure 44. Initialization with built-in Booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0], TC, M[1:0] for Normal Display Operation
Switch "ON" Booster and Display Control Logic (PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
Figure 45. Dual Partial Display Enabling Instruction Flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address SET 2nd Sector Start Address
OPTIONAL1
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
35/51
STE2002
Figure 46. Dual Partial Display Mode configuration or Duty Change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] for Partial Display Operation
SET Partial Display Configuration (PD[2:0]) SET 1st Sector Start Address SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
36/51
STE2002
Figure 47. DATA RAM to display Mapping
DISPLAY DATA RAM
bank 0
GLASS TOP VIEW
bank 1
DISPLAY DATA RAM = "1" DISPLAY DATA RAM = "0"
bank 2
LCD
bank 3
bank 7
bank 8
ICOR ROW
D00IN1155
Table 15. Test Pin Configuration
Test Numb. TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 TEST_8 TEST_9 TEST_10 TEST_11 TEST_12 TEST_13 TEST_14 Pin Configuration OPEN
GND
GND
37/51
STE2002
ABSOLUTE MAXIMUM RATINGS
Symbol VDD1 VDD2 VLCD ISS Vi Iin Iout Ptot Po Tj Tstg Supply Voltage Range Supply Voltage Range LCD Supply Voltage Range Supply Current Input Voltage (all input pads) DC Input Current DC Output Current Total Power Dissipation (Tj = 85C) Power Dissipation per Output Operating Junction Temperature Storage Temperature Parameter Value - 0.5 to + 5 - 0.5 to + 7 - 0.5 to + 12 - 50 to +50 -0.5 to VDD2 + 0.5 - 10 to + 10 - 10 to + 10 300 30 -40 to + 85 - 65 to 150 Unit V V V mA V mA mA mW mW C C
ELECTRICAL CHARACTERISTICS DC OPERATION (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11 V; Tamb =-40 to 85C; unless otherwise specified)
Symbol Supply Voltages VDD1 VDD2 VLCDIN I(VDD1) Supply Voltage Supply Voltage LCD Supply Voltage note 9 LCD Voltage Internally generated LCD Voltage Supplied externally Internally generated; note 1 VDD1 = 2.8V; VLCD = 7.6V; fsclk = 0;Tamb = 25C; note 3. VDD1 = 2.8V; VLCD = 7.6V; fsclk = 1Mhz;Tamb = 25C; note 3, 8. OSC_IN=GND; parallel port I(VDD2) Voltage Generator Supply Current with VOP = 0 and PRS = [0:0] with external VLCD VDD2= 2.8V;VLCD=7.6V; fsclk= 0; Tamb = 25C; no display load; 4x charge pump; note 2,3,6, I(VDD1,2) Total Supply Current VDD1,VDD2= 2.8V; VLCD = 7.6V; 4x charge pump; fsclk = 0;Tamb = 25C; no display load; note 2,3,6 Power down Mode with internal or External VLCD. Note 4 I(VLDCIN) External LCD Supply Voltage Current Logic Outputs V0H VOL High logic Level Output Voltage Low logic Level Output Voltage IOH=-500A IOL=500A 0.8VDD1 VSS VDD1 0.2VDD1 V V VDD =2.8V; VLCD =7.6V;no display load; fsclk = 0; Tamb = 25C; note 3. 5 10 1.7 1.75 4.5 4.5 15 20 120 3.6 4.2 11 11 30 150 V V V V A A Parameter Test Condition Min. Typ. Max. Unit
VLCDOUT LCD Supply Voltage Supply Current
1 35
A A
25
65
A
3 10
5 15
A A
38/51
STE2002
ELECTRICAL CHARACTERISTICS (continued) DC OPERATION (VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11 V; Tamb =-40 to 85C; unless otherwise specified)
Symbol Logic Inputs VIL VIH Iin VIL VIH Logic LOW voltage level Logic HIGH Voltage Level Input Current Logic LOW voltage level Logic HIGH Voltage Level Vin = VSS1 or VDD1 VSS 0.7VDD1 -1 VSS 0.7VDD1 0.3VDD1 VDD2 1 0.3VDD1 VDD1 +0.5V 3K 5K -50 -50 VDD = 2.8V; VLCD = 10V; fsclk=0; Tamb=25C; no display load; note 2, 3, 6 & 7; VOP = 61h, PRS = 2hex -1.5 5K 10K +50 +50 1.5 V V A V V Parameter Test Condition Min. Typ. Max. Unit
Logic Inputs/Outputs
Column and Row Driver Rrow Rcol Vcol Vrow VLCD ROW Output Resistance Column Output resistance Column Bias voltage accuracy Row Bias voltage accuracy LCD Supply Voltage accuracy; Internally generated VLCD = 10V; VLCD = 10V; No load kohm kohm mV mV %
LCD Supply Voltage
TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
Notes: 1. 2. 3. 4. 5. 6.
Temperature coefficient
-0.0*10-3 -0.35*10-3 -0.7*10-3 -1.05*10-3 -1.4 *10-3 -1.75*10-3 -2.1*10-3 -2.3*10-3
1/C 1/C 1/C 1/C 1/C 1/C 1/C 1/C
The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. Internal clock When fsclk = 0 there is no interface clock. Power-down mode. During power-down all static currents are switched-off. f external VLCD, the display load current is not transmitted to IDD Tolerance depends on the temperature; (typically zero at T amb = 27C), maximum tolerance values are measured at the temperature range limit. 7. For TC0 to TC7 8. Data Byte Writing Mode 9.VDD1 VDD2
39/51
STE2002
ELECTRICAL CHARACTERISTICS AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85C; unless otherwise specified)
Symbol FOSC FEXT FFRAME Tw(RES) TLOGIC
(RES)
Parameter Internal Oscillator frequency External Oscillator frequency Frame frequency RES LOW pulse width Reset Pulse Rejection Internal Logic Reset Time VDD1 vs. VDD2 Delay
Test Condition VDD = 2.8V; Tamb = -20 to +70 C
Min. 64 20
Typ. 72
Max. 80 100
Unit kHz kHz Hz s
INTERNAL OSCILLATOR
fosc or fext = 72 kHz; note 1 5
75 1 5 0
s s s
TVDD
Figure 48. RESET timing diagram
Tw(res) Tlogic(res)
VDD2
VDD1
RES
INPUTS I/O (HOST)
I/O (DRIVER) INTERFACE OUTPUT
Hi-Z
Hi-Z
OSCIN (HOST)
OSC OUT (DRIVER)
BSY FLG
RESET TABLE LOADED
LR0118
40/51
STE2002
ELECTRICAL CHARACTERISTICS AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85C; unless otherwise specified)
Symbol I2C Parameter Test Condition Min. Typ. Max. Unit BUS INTERFACE (See note 4) SCL Clock Frequency Fast Mode High Speed Mode; Cb=100pF (max);VDD1=2 High Speed Mode; Cb=400pF (max); VDD1=2 Fast Mode; VDD1=1.7V TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT Tr;CL TrCL1 Set-up time (repeated) START condition Hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock Data set-up time Data hold time Rise time of SCLH signal Note 2, 3, Cb=100pF Note 2, 3, Cb=100pF Note 2, 3, Cb=100pF Note 2, 3, Cb=100pF Note 2, 3, Cb=100pF Note 2, 3; Cb=100pF Note 2, 3; Cb=100pF 160 160 160 60 10 40 10 10 DC DC DC 400 3.4 1.7 400 kHz MHz MHz KHz ns ns ns ns ns ns ns ns
FSCL
Rise time of SCLH signal after a Note 2, 3, Cb=100pF repeated START condition and after an acknowledge bit Fall time of SCLH signal Rise time of SDAH signal Fall time of SDAH signal Rise time of SDAH signal Fall time of SDAH signal Set-up time for STOP condition Capacitive load for SDAH and SCLH Capacitive load for SDAH + SDA line and SCLH + SCL line Note 2, 3, Cb=100pF Note 2, 3, 4, Cb=100pF Note 2, 3, 4, Cb=100pF Note 2, 3, 4, Cb=400pF Note 2, 3, 4, Cb=400pF Note 2, 3, Cb=100pF
TfCL TrDA TfDA TrDA TfDA TSU;STO Cb Cb
10 10 10 20 20 160 100 400 400 160 80
ns ns ns ns ns ns pF pF
Figure 49. I2C-bus timings
Sr tfDA trDA Sr P
SDAH tHD;DAT tSU;STA SCLH tfCL trCL tHIGH tLOW
= MCS current source pull-up
tSU;DAT
tHD;STA
trCL1
(1)
trCL1
(1)
tLOW tHIGH
D00IN1153
= Rp resistor pull-up
41/51
STE2002
ELECTRICAL CHARACTERISTICS (continued) AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85C; unless otherwise specified)
Symbol TCY(EN) TW(EN) TSU(A) TH(A) TSU(D) TH(D) TSU(D) THU(D) Parameter Enable Cycle Time Enable Pulse width Address Set-up Time Address Hold Time Data Set-Up Time Data Hold Time Data Set-Up Time in read Mode Data Hold Time In Read mode 100 Test Condition VDD1 = 1.7V; Write; note 2, 6 Min. 150 60 30 40 30 30 100 Typ. Max. Unit ns ns ns ns ns ns ns ns PARALLEL INTERFACE
Figure 50. Parallel interface Write timing
PD/C tSU(A) E tSU(D) tHO(D) tCY(en) DB0-DB7 tW(en) th(A)
R/W WRITE
Figure 51. Parallel interface Read timing
PD/C tSU(A) E tSUR(D) tHOR(D) tCY(en) Don't Care tW(en) th(A)
DB0-DB7
R/W
READ
42/51
STE2002
ELECTRICAL CHARACTERISTICS (continued) AC OPERATION (VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 11V; Tamb =-40 to 85C; unless otherwise specified)
Symbol SERIAL INTERFACE TCYC TPWH1 TPWL1 TS2 TH2 TPWH2 TS3 TH3 TS4 TH4 TS5 TH5 TH6 Clock Cycle SCLK SCLK pulse width HIGH SCLK Pulse width LOW SCE setup time SCE hold time SCE minimum high time SD/C setup time SD/C hold time SDIN setup time SDIN hold time SOUT Access Time SOUT Disable Time vs. SCLK SOUT Disable Time vs. SCE VDD1 = 1.7V; Write; note 2, 6 150 60 60 30 50 50 30 40 30 40 100 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Test Condition Min. Typ. Max. Unit
Figure 52. Serial interface Timing
tS2 CS tS3 D/C tH3
tH2
tPWH2
tCYC tPWL1 SCLK tS4 SDIN tS5 SOUT
LR0001
tWH1 tS2
tH4
tH5
tH6
Notes: 1. F fra me = --------960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with an input voltage swing of VSS to VDD 3. Cb is the capacitive load for each bus line. 4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 5. CVLCD is the filtering Capacitor on VLCDOUT 6. T rise and T fall (30%-70%) = 10 ns
f osc
43/51
STE2002
Table 16. Pad Coordinates
NAME C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 X (m) -3275.0 -3225.0 -3175.0 -3125.0 -3075.0 -3025.0 -2975.0 -2925.0 -2875.0 -2825.0 -2775.0 -2725.0 -2675.0 -2625.0 -2575.0 -2525.0 -2475.0 -2425.0 -2375.0 -2325.0 -2275.0 -2225.0 -2175.0 -2125.0 -2075.0 -2025.0 -1975.0 -1925.0 -1875.0 -1825.0 -1775.0 Y(m) -946.5 -946.11 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5
Table 16. Pad Coordinates (continued)
NAME C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 PAD 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 X (m) -1725.0 -1675.0 -1625.0 -1575.0 -1525.0 -1475.0 -1425.0 -1375.0 -1325.0 -1275.0 -1225.0 -1175.0 -1125.0 -1075.0 -1025.0 -975.0 -925.0 -875.0 -825.0 -775.0 -725.0 -675.0 -625.0 -575.0 -525.0 -475.0 -425.0 -375.0 -325.0 -275.0 -225.0 Y(m) -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5
44/51
STE2002
Table 16. Pad Coordinates (continued)
NAME C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 PAD 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 X (m) -175.0 -125.0 +125.0 +175.0 +225.0 +275.0 +325.0 +375.0 +425.0 +475.0 +525.0 +575.0 +625.0 +675.0 +725.0 +775.0 +825.0 +875.0 +925.0 +975.0 +1025.0 +1075.0 +1125.0 +1175.0 +1225.0 +1275.0 +1325.0 +1375.0 +1425.0 +1475.0 +1525.0 Y(m) -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5
Table 16. Pad Coordinates (continued)
NAME C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 PAD 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 X (m) +1575.0 +1625.0 +1675.0 +1725.0 +1775.0 +1825.0 +1875.0 +1925.0 +1975.0 +2025.0 +2075.0 +2125.0 +2175.0 +2225.0 +2275.0 +2325.0 +2375.0 +2425.0 +2475.0 +2525.0 +2575.0 +2625.0 +2675.0 +2725.0 +2775.0 +2825.0 +2875.0 +2925.0 +2975.0 +3025.0 +3075.0 Y(m) -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5 -946.5
45/51
STE2002
Table 16. Pad Coordinates (continued)
NAME C124 C125 C126 C127 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 PAD 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 X (m) +3125.0 +3175.0 +3225.0 +3275.0 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 Y(m) -946.5 -946.5 -946.5 -946.5 -875.0 -825.0 -775.0 -725.0 -675.0 -625.0 -575.0 -525.0 -475.0 -425.0 -375.0 -325.0 -275.0 -225.0 -175.0 -125.0 -75.0 -25.0 +25.0 +75.0 +125.0 +175.0 +225.0 +275.0 +325.0 +375.0 +425.0
Table 16. Pad Coordinates (continued)
NAME R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80/ICON TEST_1 TEST_2 TEST_3 TEST_4 TEST_5 TEST_6 TEST_7 TEST_8 TEST_9 TEST_10 VSSAUX SA1 SA0 EXT SEL2 SEL1 ICON_MODE PAD 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 X (m) +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3571.5 +3275.0 +3225.0 +3175.0 +3125.0 +3075.0 +2825.0 +2775.0 +2725.0 +2675.0 +2625.0 +2575.0 +2525.0 +2475.0 +2425.0 +2375.0 +2225.0 +2175.0 +2125.0 +2075.0 +2025.0 +1975.0 +1925.0 Y(m) +475.0 +525.0 +575.0 +625.0 +675.0 +725.0 +775.0 +825.0 +875.0 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5
46/51
STE2002
Table 16. Pad Coordinates (continued)
NAME OSC_IN VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 BUSY_FLAG SDOUT SDIN SD/C SCE SCLK PAD 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 X (m) +1875.0 +1825.0 +1825.0 +1775.0 +1775.0 +1725.0 +1725.0 +1675.0 +1675.0 +1625.0 +1625.0 +1575.0 +1575.0 +1525.0 +1525.0 +1475.0 +1475.0 +1425.0 +1425.0 +1375.0 +1375.0 +1325.0 +1325.0 +1275.0 +1275.0 +1125.0 +975.0 +925.0 +875.0 +825.0 +775.0 Y(m) +946.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5
Table 16. Pad Coordinates (continued)
NAME VSSAUX R/W D7 D6 D5 D4 D3 D2 D1 D0 PD/C E RES VSSAUX SDA_OUT SDA_OUT SDA_IN SCL VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 PAD 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 X (m) +625.0 +575.0 +525.0 +475.0 +425.0 +375.0 +325.0 +275.0 +225.0 +175.0 +125.0 +75.0 -75.0 -225.0 -275.0 -325.0 -375.0 -425.0 -975.0 -975.0 -1025.0 -1025.0 -1075.0 -1075.0 -1125.0 -1125.0 -1175.0 -1175.0 -1225.0 -1225.0 -1275.0 Y(m) +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5
47/51
STE2002
Table 16. Pad Coordinates (continued)
NAME VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 TEST_11 TEST_12 TEST_13 TEST_14 OSC_OUT VLCDIN_1 VLCDIN_2 VLCDIN_3 VLCDIN_4 VLCDIN_5 VLCDIN_6 VLCDIN_7 VLCDIN_8 VLCDIN_9 VLCDIN_10 VLCDSENSE_1 VLCDSENSE_2 VLCDOUT_1 VLCDOUT_2 VLCDOUT_3 VLCDOUT_4 VLCDOUT_5 VLCDOUT_6 VLCDOUT_7 PAD 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 X (m) -1275.0 -1325.0 -1325.0 -1375.0 -1375.0 -1425.0 -1425.0 -1475.0 -1525.0 -1575.0 -1625.0 -2175.0 -2325.0 -2325.0 -2375.0 -2375.0 -2425.0 -2425.0 -2475.0 -2475.0 -2525.0 -2525.0 -2575.0 -2575.0 -2625.0 -2625.0 -2675.0 -2675.0 -2725.0 -2725.0 -2775.0 Y(m) +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +946.5 +946.5 +946.5 +946.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5 +839.5 +946.5
Table 16. Pad Coordinates (continued)
NAME VLCDOUT_8 VLCDOUT_9 VLCDOUT_10 R39 R38 R37 R36 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 PAD 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 X (m) -2775.0 -2825.0 -2825.0 -3075.0 -3125.0 -3175.0 -3225.0 -3275.0 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 Y(m) +839.5 +946.5 +839.5 +946.5 +946.5 +946.5 +946.5 +946.5 +875.0 +825.0 +775.0 +725.0 +675.0 +625.0 +575.0 +525.0 +475.0 +425.0 +375.0 +325.0 +275.0 +225.0 +175.0 +125.0 +75.0 +25.0 -25.0 -75.0 -125.0 -175.0 -225.0
48/51
STE2002
Table 16. Pad Coordinates (continued)
NAME R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 ICON PAD 311 312 313 314 315 316 317 318 319 320 321 322 323 X (m) -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 -3571.5 Y(m) -275.0 -325.0 -375.0 -425.0 -475.0 -525.0 -575.0 -625.0 -675.0 -725.0 -775.0 -825.0 -875.0 Bumps on Two Rows Size Pad Size Pad Pitch X -3574.5 +3574.5 -2250 +1200 Y -949.5 -949.5 +949.5 +949.5 MARKS mark1 mark2 mark3 mark4 Wafers Thickness 500m Spacing between Bumps 1-323 20m Bumps on Single Row Size 1-187 212-235 256-260 283-323 188-211 236-255 261-282 1-323 1-323 30m X 98 m X 17.5
94 m 39 m
Figure 54. Alignment marks dimensions
Table 17. Bumps
Bump Number Dimensions
30m X 87 m X 17.5
Figure 53. Alignment marks coordinates
43m X 107m 50m
Table 18. Die Mechanical Dimensions
Die Size 2.07mm x 7.32mm
49/51
STE2002
Figure 55. DIE ORIENTATION IN TRAY
DIE IDENTIFICATION
Mark 3 Mark 1
STE2002
Mark 4 Mark 2
Figure 56. TRAY INFORMATION
A
A
Array Size = 13 x5 (65) Units
50/51
STE2002
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
(R)
51/51

▲Up To Search▲

Price & Availability of STE2002

	To Download STE2002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .